June 02, 2008

New FPGA meets handheld price, power, and space requirements

New company SiliconBlue has created, from the ground-up, a family of FPGAs that meets the unique price, power, and space requirements associated with handheld products.

By John Birkner and Ibrahim Khozam, SiliconBlue

Handheld, battery-powered applications could significantly benefit from the time-to-market advantages that FPGAs have brought to wall-plugged consumer, computer, and industrial electronics. The price, power, and space requirements of handheld devices, however, have limited the use of programmable logic to small applications such as voltage-level-translation and port enhancement. Finally, a solution is now available that meets the power and logic capacity requirements that handheld designers have been waiting for. SiliconBlue has created, from the ground-up, a family of FPGAs that meets these unique handheld requirements.

1. NVCM enables lowest price, power, and space in new FPGA technology.

Non-volatile configuration memory (NVCM)
A conventional SRAM-based FPGA requires a two-chip solution, because the configuration is performed at power-up typically using an external Flash PROM as illustrated in Fig 2.

2. Classic SRAM FPGAs are configured from external sources on power-up.

Two chips cost more than one chip, they consume more power, and they occupy more space. Thus, the foundation technology that enables the lowest price, power and space associated with SiliconBlue's ground-up FPGA design is Non-Volatile Configuration Memory (NVCM) on a 65 nm low power CMOS process. Using a standard process from TSMC, the NVCM is embedded into an SRAM FPGA (Fig 3).

3. SiliconBlue SRAM FPGAs are configured from on-chip, embedded NVCM, saving cost, power and space.

As the embedded NVCM area is less than 3% of the total chip area, the total cost of the single chip solution, is much lower than the two-chip solution. Compared to non-volatile PLDs on older 130 nm and 180 nm flash processes, SiliconBlue's 65 nm NVCM provides the lowest cost-per-unit-logic and will continue to lead as the NVCM is scalable to 40 nm and beyond.

Low-power process
SRAM FPGAs have dominated programmable logic due to the low cost afforded by leading-edge, high-performance process nodes. Now, SiliconBlue is applying this leading-edge strategy to handheld FPGAs by utilizing TSMC's 65nm LP (low-power) process node. Previous leading process nodes were high-performance and high-power, and therefore were not suitable for handheld requirements. Beginning at 65 nm, however, the trend has switched to low-power as the first available on a new process node.

Advantages of the leading process node are, of course, smaller transistors, providing higher logic capacity and lower capacitance at a lower core voltage, resulting in lower active power, proportional to CV². Higher logic capacity translates into lower cost per unit logic than older process nodes.

Power modes defined by handset designer
SiliconBlue uses the same definitions for power modes as handset designers. First, the Operating Mode refers to normal operation in the MHz range where the handheld device is performing a specific operation. Second, the Stand-by Mode is the power saving mode operating in the kHz range, where the handheld device is waiting for the next operation to be called. Typically, in Stand-by mode, operation is at 32 kHz supplied by the real time clock. These handheld modes are detailed in Table 1.

Table 1. Definition and comparison of power modes.

SiliconBlue specifies power for Operation as Active Fast Power (AFP). At 32 MHz, the iCE65L04 device consumes 9 mW compared to competing SRAM FPGAs devices at 60 to 62 mW and other PLDs at 30 to 170 mW. Clearly, competing SRAM FPGAs consume too much power to be used in handheld devices. For example, a 60 mW FPGA with 1.2V core would consume the entire capacity of a 1000 mA hour battery in less than 20 hours.

SiliconBlue specifies power for Stand-by as Active Slow Power (ASP). At 32 kHz, the iCE65L04 device consumes 0.025 mW compared to competing SRAM FPGAs devices at 30 to 36 mW and other PLDs at 0.044 to 0.350 mW. Again, at 30 to 36 mW, competing SRAM FPGAs consume too much power to be used in handheld devices. Compared to other PLDs, the iCE65L04 device consumes significantly less Stand-by power.

Other PLD suppliers specify Static modes of operation with the clock stopped at 0 MHz. In the real world, these modes are rarely used by handset designers as they require additional hardware and software resources to stop the clock. The preferred method of Stand-by is to keep the heartbeat alive at 32 kHz, awaiting the next operation such as detecting a keypad click.

Other PLD suppliers also specify Power Down modes such as sleep, hibernate, and freeze, where state is maintained while functionality is disabled. Once again, these modes are rarely used by handset designers as they require additional hardware and software resources. Furthermore, there is a paradox here. PLDs are often used in control and power management. How can the PLD wake itself up when its functionality is disabled? Additionally, these modes require recovery time to wake up, further complicating design.

Underlying SRAM FPGA architecture
SiliconBlue utilizes a standard, mature, SRAM based 4-input LUT architecture that is optimized for lowest power. Transistor parameters are selected for lowest leakage, enabling 25 µW operation at 32 kHz for the iCE65L04 containing 4k Logic Cells. Where high performance is required, such as in the arithmetic carry path, faster transistors with higher leakage are employed, however, these circuits are powered down when not used. Full CMOS complimentary design is utilized in the LUT and routing architecture, minimizing leakage throughout the design.

Block RAMs consuming less than 0.5 µA per 4 k-bit block are implemented with low leakage, low power, two-port register file IP from TSMC's standard ASIC LP65 IP library. I/O drivers for banks 0, 1, and 2 utilize the TSMC 65 standard I/O while bank 3 utilizes TSMC 65 nm low power memory I/O library to provide LVDS and Mobile DDR I/O capability. This use of standard ASIC IP enables SiliconBlue to move quickly to provide new features to customers and quickly migrate next generation FPGA architecture to the 40 nm process node and beyond.

Application IP
Basic functions for programmable logic begin with voltage level translation and IO Pin expansion, interfacing incompatible devices. More complex functions include interfacing applications and media processors to memory, SD flash memory cards, displays, touch screens, and keypads using interface standards such as I2C, SPI and UART. Custom functions range from image rendering to MP3 Audio buffer co-processing to extend battery life.

Standard IP available from SiliconBlue includes the following:

Table 2. Application IP.

Reference design applications IP example: Picture Frame
FPGAs are becoming more practical and applicable in multimedia applications. However, the application of FPGAs as co-processors has been ruled out of consumer handheld designs because of high power consumption. Today, with SiliconBlue Ultra Low Power technology, designers can find high density FPGAs, functioning at ultra low power consumption, while processing graphics and rendering images.

Application processors have three different power modes at a minimum and seven power modes at maximum. Using an application processor produces excessive burden on the designer and the application in price, power, and space. With iCE FPGAs, designers have the option of using an ultra-low power device, constantly active, to implement advanced IP.

SiliconBlue has developed a Digital Picture Frame IP that was prototyped using a QVGA display with an 8-bit serial interface. The display is a 3.6 inch digital panel module equipped with a Topology compact TFT LCD module. The design was implemented using the SiliconBlue iCEman65 development platform connected to the LCD via the iCEman expansion port. The Digital Picture Frame is a fully autonomous IP module: 0% CPU load through use.

The application was developed using readily available IP blocks such as SPI and RGB display interface. Fig 4 shows the various IP blocks used to implement the digital picture frame design.

4. Image frame buffering using an iCE04 FPGA.
(Click this image to view a larger, more detailed version)

SPI Master: SPI interface block to the external serial flash. This interface is used to load the configuration bits and obtain the picture frame data for buffering.

SPI Interface Control: SPI interface allowing overlay characters on screen and selection of various pictures to be buffered and displayed.

CMD and Character Memory: Block RAM used to store user input in pre-processing phase.

Control State Machine: State machine controlling and scheduling events necessary for image rendering.

Character Processor: Overlays characters on the picture. It also contains an internal ROM memory.

Line FIFO: Line buffer storing one line before transmitting it to the LCD display.

Display Serial Control: LCD module interface block generating control signals and necessary vertical and horizontal synchronization signals to the LCD module.

The utilization for the iCE04 device in this example is illustrated in Table 3.

Table 3. iCEL04 utilization for the digital Picture Frame.

5. Picture Frame graphics co-processor FPGA consumes less than 1 mA on core voltage.
(Click this image to view a larger, more detailed version)

Summary
SiliconBlue has built from ground up, the first single-chip, reprogrammable, ultra-low power FPGA optimized for handheld, mobile applications. While conventional SRAM FPGA vendors have focused on speed, density, and features, SiliconBlue has set a new standard for price, power and space.

SiliconBlue is the first company to combine low-power, Non-Volatile Configuration Memory (NVCM) and standard SRAM technologies at the 65 nm LP process node. The process is scalable to 40 nm and beyond.

John Birkner is VP of Strategic Marketing at SiliconBlue. John has over 30 years of experience in the field of semiconductors as well as programmable logic. He was the Co-Founder and Chief Technical Officer at QuickLogic Corporation and has also worked with MMI and Xilinx.

John has 24 patents in the field of programmable logic including the original PAL patent, and holds a Masters degree from the University of Akron and a bachelor's degree from the University of California, Berkeley.

Ibrahim Khozam is System Applications Engineer at SiliconBlue. Prior to joining SiliconBlue, Ibrahim was an FAE (Field Applications Engineer) at Marvell Semiconductor focusing on their applications processors.

In addition, Ibrahim worked in system design at Intel Corporation within the company's Xscale processor product line. Ibrahim holds both undergraduate and masters degrees in computer engineering from San Jose State University, where he graduated with honors.