Low Power Design
 
FPGAs as ASSP/Microcontroller Helpers – When ASICs and SOCs Won’t Do
Steve Leibson
Tuesday 01 September 2009
 
Without doubt, an ASIC or SOC is the way to create systems with the lowest power dissipation. However, many other factors can mitigate the advantages of custom system silicon. Those factors include a critical and looming market window, a lack of funds for the resulting ASIC/SOC NRE charges and design-tool costs, a design team that simply lacks experience with chip design, or inadequate projected sales volumes to justify the time and expense of ASIC/SOC design. In such circumstances, the design team will usually try to find an ASSP (application-specific standard product) or an off-the-shelf microcontroller that closely meets the design specs and will then fill the inevitable functional gaps with software or firmware.
 
But what if that’s not possible? What if there is no such ASSP or microcontroller? What if software can’t fill the gap? Then the only choice is to get the hardware as close as possible and then plug the gap with additional circuitry. But extra circuitry brings added disadvantages. First, it adds to the BOM, assembly, and unit-test costs. Second, it consumes space on the circuit board and in applications that are really short on room (such as mobile phone handsets) it consumes additional cubic millimeters that probably cannot be spared. Finally, it consumes added power.
 
Enter the FPGA vendors, who would have you believe that one of their components can save the day by adding huge numbers of “system gates” at low cost. You can get both large gate counts and low price from FPGAs, but rarely at the same time. Further, FPGAs with large gate counts have large accompanying power-consumption specs. That’s because the major FPGA vendors have pursued performance over all other characteristics and their static- and dynamic-power consumption specs reflect that chase. As FPGAs have become IC process-technology drivers, they have continued to push lithography limits using performance-tuned process parameters. The resulting FPGAs make the most of process speed at the cost of dynamic current consumption and high leakage.
 
However, if all you’re doing with the FPGA is making relatively simple additions to an ASSP or microcontroller, you may need an FPGA tuned for a different design approach. That’s the philosophy behind SiliconBlue Technology’s iCE65 FPGAs, which employ a low-leakage, albeit slower version of TSMC’s 65nm process to produce low-cost FPGAs (on the order of a buck or two) with microwatt power requirements at moderate gate capacities (a few thousand 4-input LUTs). These small, low-power FPGAs are designed to be ASSP/Microcontroller helpers. They’re designed to allow the needed customization while relegating most of a system to a well-optimized standard chip or chip set.
 
What can you use such devices for? I asked that of Denny Steele, SiliconBlue’s Director of Marketing and Applications. Here’s the list he reeled off the top of his head:
 
  • An interrupt queue for a GUI-driven application to reduce the frequency that software must bring a host processor out of sleep mode thus minimizing processor power consumption
  • A port multiplexer to add an extra SD memory card to an ASSP with only one storage port
  • A buffered port switch to allow host and application processors to share storage media such as an SD card
  • An interface adapter that allows an existing LCD interface port to communicate with a different sort of display—such as an ePaper or eInk display that has radically different timing requirements
  • A parallel-to-serial or serial-to-parallel converter to mate one type of display interface to the other
  • An display-format converter so that an ASSP/microcontroller designed for one display size can more easily control displays of other sizes
  • A cafeteria of virtual, configurable legacy interfaces that aren’t all needed for any one design but are needed over the full usage spectrum for the final hardware design
 
Of course, these are just a few of the application ideas for an ASSP/microcontroller helper in the form of an FPGA. Significantly, the FPGA system-augmentation design path can help when product life cycles are quite short, as they are for mobile phone handsets in the developed world (as it so happens, outside of the US in the case of cellular telephony). In such markets, product life cycles are measured in months and design teams may be creating three or four designs per year.
 
An FPGA-augmented design based on standard handset chip sets comes in quite handy in such situations because the FPGA can be used to add features that end-users notice such as enhanced display resolution, touch screens, extra SD or SIM cards, and so on. Such desirable features prompt customers to unsheathe their credit cards. One board-level design with FPGA augmentation can accommodate more than one product design and more than one product generation without requiring a BOM change. That’s a real competitive advantage in today’s quick-turn world of consumer electronics.
 
Consequently, this is the world for which SiliconBlue optimized its iCE65 FPGA. The device is tiny—as small as 3×4 mm—to fit in small, handheld consumer products. A 4000-LUT iCE65 device draws a mere 15 microamps at 1V when running at 32 KHz, the standard heartbeat of a mobile phone handset in standby mode. That’s slow enough to use very little power but fast enough to catch an event that merits waking the host processor. Of course, the FPGA can run much faster, with higher resulting dynamic power consumption.
 
Are these low-cost, low-power, small-size optimizations enough to create a niche for SiliconBlue in the fiercely competitive FPGA market? “We’re betting the farm that customers will want to do this” replied Steele.
 
© 2009 SiliconBlue Technologies Corporation