ASIC-like Cost

SiliconBlue has carefully architected its iCE65™ mobileFPGA™ devices to target high volume, battery powered applications where low cost, small form factor, and low power are key.

Creating cost efficient devices requires a specific design approach. For the iCE65 mobileFPGA family, SiliconBlue started by determining the ideal number of user I/O pins required to support common functions in handheld applications. Using this information, each member of the family was then designed with the optimal target I/O. This approach is very similar to how Application Specific Integrated Circuits (ASICs) are designed.

Cost-focused devices such as ASICs are "pad-limited". Pad limited means that the die area is determined by the perimeter created by the I/O pads that are organized as a ring around the periphery of the die. Therefore, the number of I/O is a driving factor for cost. With smaller silicon geometries you are able to achieve more logic density within the perimeter, but this does not drive cost since I/O pads tend not to benefit greatly from smaller geometry.

Conversely, many traditional FPGAs are core-limited, since they are typically designed to maximize logic capacity. This approach inherently places traditional FPGAs at a disadvantage compared to ASICs. For example, if a design exactly fills a traditional core-limited FPGA, it can be concluded that the die size of the equivalent ASIC will be significantly smaller, due to the fact that since ASIC gates are much more area efficient than FPGA gates. This places traditional core-limited FPGAs at an inherent cost disadvantage.

Figure 1 - SiliconBlue's pad-limited iCE65 mobileFPGA devices are able to achieve ASIC-like costs compared to traditional FPGAs.

By designing its mobileFPGAs to be pad-limited, SiliconBlue's iCE65 devices can truly be called ASIC-like. Cost management is an important element of SiliconBlue's strategy to target handheld applications.

ASIC-like Cost

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