Advanced Package Technology

Package technology is a key part of SiliconBlue's strategy to offer handheld application designers the very best solution possible. By using the most advanced ball-grid array (BGA), quad-flat pack, and wafer-level chip scale (WLCSP) packaging, iCE65™ mobileFPGA™ devices support the smallest footprint possible.

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Wafer Level Chip Scale Packaging

SiliconBlue's iCE65 mobileFPGA devices offer the industry's only true Wafer-Level Chip Scale Packaging (WLCSP). WLCSP refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. WLCSP is a true chip-scale packaging technology, since the resulting package is practically the same size as the die.

WLCSP extends the wafer fab process to include the addition of device interconnect and device protection. SiliconBlue uses a redistribution layer and bump technology, which adds to the additional fab process with a step that deposits a multi-layer thin-film metal rerouting and interconnection system to each device on the wafer. This is achieved using the same standard photolithography and thin film deposition techniques employed in the device fabrication itself.

This additional level of interconnection redistributes the peripheral bonding pads of each chip to an area array of underbump metal pads that are evenly deployed over the chip's surface. The solder balls or bumps used in connecting the device to the application circuit board are subsequently placed over these pads.

Aside from providing the WLCSP's means of external connection, this redistribution technique also improves chip reliability by allowing the use of larger and more robust balls for interconnection and better thermal management of the device's I/O system.

The first layer put over the wafer to 'package' the device is a polymer dielectric to isolate the device circuitry from the rewiring system. The rewiring metallization layer is then deposited over this dielectric. This layer is then covered by another dielectric layer, which serves as the solder mask. Under bump metallization is then put over the positions to be subsequently occupied by the solder balls.

After the balls have been attached, flip-chip techniques are used to mount the WLP device onto the circuit board.

Source: www.siliconfareast.com

By using WLCSP technology, iCE65 mobileFPGAs offer very small footprints as low as 6.25mm², and eliminate standard plastic package costs.


Figure 1 - Wafer Level Chip Scale Packaging (WLCSP) enables standard mounting balls to be attached directly to the die via a redirection layer	Figure 2 - WLCSP devices minimize board space and device costs.

Small Footprint Packages

Silicon Blue offers a variety of small footprint packages including quad flat pack no lead (QN) and chip scale micro ball grid array (CB) that offer the highest logic capacity per square millimeter.

Figure 3 - shows the advanced small footprint packages offered by SiliconBlue Technologies.

Advanced Package Technology

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