Ultra-Low Power Technology

For battery operated handheld applications, power consumption is a vital characteristic that needs to be aggressively managed for success. Battery life is often a differentiating feature for these types of products. SiliconBlue's iCE65™ mobileFPGA™ devices have been designed to minimize static and active current consumption, providing designers with a logic device platform that specifically meets their needs.

SiliconBlue's power management approach focuses on two major areas: At a transistor level, we minimize gate dielectric tunneling leakage by careful process selection, and we manage the gate length of the transistors used in our devices. At an architectural level, we employ many of the common techniques used in logic devices, such as turning off clocks to unused areas of the device. In addition, we offer the user the ability to control factors such as supply voltage and clock gating to further manage power for any given application.

Gate dielectric leakage occurs due to tunneling current flowing through the area of the gate (W x L) to the substrate. The mechanism for this leakage is quantum tunneling, understood since 1928, yet it has proven to be a difficult problem for foundries and electronic circuit designers to solve. To optimize transistor switching characteristics and power consumption, three factors must be balanced: dielectric thickness, its energy barrier height, and its dielectric constant (K).

Figure 2 and Figure 3 illustrate the effect different gate dielectric thicknesses have on tunneling leakage.

Figure 2 - Negligible tunneling current if gate dielectric is thick.

High tunneling current if gate dielectric is thin

Figure 3 - High tunneling current if gate dielectric is thin.

The 65-nm CMOS process that SiliconBlue has chosen contains elements in the gate dielectric that increase the dielectric constant yet retain a high energy barrier. As a consequence, gate leakage current is greatly reduced and the transistor speed is maintained.

Choosing the ideal gate length requires an assumption of drive strength, and then subsequently an analysis of the other sources of leakage current: off-state source-to-drain leakage, and PN junction leakage.

Careful control of off-state, source-drain leakage and PN junction leakage is critical in reducing overall leakage current. Off-state leakage is inversely proportional to the gate length. However, PN Junction leakage is proportional to the gate length (see Fig. 1). If a very short gate length is chosen, the transistor will be very fast, but the circuit will waste supply current in the off state due to high source-drain leakage. However, if a longer gate length is chosen, PN junction and gate dielectric leakage tend to dominate, and the transistor's speed and responsiveness are reduced.

Figure 1 overlays these behaviors and conceptually depicts the strategy that SiliconBlue has employed to select optimal gate lengths. By taking this approach, iCE65 mobileFPGA devices strike a perfect balance between these characteristics to meet the performance needs of handheld applications while minimizing the power required to operate the device.

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